In the current electronic system, industry insiders use a Gigabit Ethernet physical layer (Gigabit Ethernet Physical layer, GEPHY) or a fast Ethernet physical layer (Fast Ethernet Physical layer, FEPHY) to refer to a circuit unit of its corresponding layer.
Generally, the GEPHY/FEPHY must include a clock generator, which is used for implementing functions such as timing and transceiving of data code streams at various transmission rates. The current clock generator of the GEPHY/FEPHY needs to cover clock signals needed at two transmission rates such as 125 MBaud (Baud) and 10 MBaud.
The clock generator disposed in the existing GEPHY/FEPHY and capable of covering the foregoing two transmission rates includes: two phase-lock loop circuits and multiple analog mixer circuits, where the two phase-lock loop circuits are disposed in parallel, and an output end of each phase-lock loop circuit is connected to an adapted analog mixer circuit, so as to output a clock signal suitable for a 125 Mbaud/10 Mbaud transmission rate through an output end of the analog mixer circuit.
However, in the existing technical solutions, multiple phase-lock loop circuits and multiple analog mixers are included, so power consumption is high and a larger chip area needs to be occupied, thereby not facilitating miniaturization of the chip and reduction of the cost of the whole chip.